This bit is set when an ADC conversion completes and the Data Registers are updated. Selected by setting the ADC Trigger Select bits, ADTS in SFIOR. The ADC will startĪ conversion on a positive edge of the selected trigger signal. When this bit is written to one, Auto Triggering of the ADC is enabled. When the conversion isĬomplete, it returns to zero. This first conversion performs initialization of the ADC.ĪDSC will read as one as long as a conversion is in progress. Same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normalġ3. The first conversion afterĪDSC has been written after the ADC has been enabled, or if ADSC is written at the Mode, write this bit to one to start the first conversion. In Single Conversion mode, write this bit to one to start each conversion. The ADC off while a conversion is in progress, will terminate this conversion. By writing it to zero, the ADC is turned off. Until this conversion is complete (ADIF in ADCSRA is set).ĪDC Control and Status Register A – ADCSRA If these bits are changed during a conversion, the change will not go in effect These bits also select the gain for the differential channels. The value of these bits selects which combination of analog inputs are connected to theĪDC.
Changing the ADLAR bit will affect the ADC Data Register immediately, Write one to ADLAR to left adjust the result. The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Used if an external reference voltage is being applied to the AREF pin. The internal voltage reference options may not be If these bitsĪre changed during a conversion, the change will not go in effect until this conversion isĬomplete (ADIF in ADCSRA is set).
These bits select the voltage reference for the ADC, as shown in Table 84.